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84320ay-01 1 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer g eneral d escription the ics84320-01 is a general purpose, dual out- put crystal-to-3.3v differential lvpecl high fre- quency synthesizer and a member of the hipercloc ks? f amily of high performance clock solutions from idt . the ics84320-01 has a se- lectable test_clk or crystal inputs. the vco operates at a frequency range of 620mhz to 780mhz. the vco frequency is programmed in steps equal to the value of the input refer- ence or crystal frequency. the vco and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. the low phase noise characteristics of the ics84320-01 make it an ideal clock source for 10 gigabit ethernet, sonet, and serial attached scsi applications. b lock d iagram p in a ssignment f eatures ? dual differential 3.3v lvpecl outputs ? selectable crystal oscillator interface or lvcmos/lvttl test_clk ? output frequency range: 77.5mhz to 780mhz ? crystal input frequency range: 14mhz to 40mhz ? vco range: 620mhz to 780mhz ? parallel or serial interface for programming counter and output dividers ? duty cycle: 49% - 51% (n > 1) ? rms period jitter: 2ps (typical) ? rms phase jitter at 155.52mhz, using a 38.88mhz crystal (12khz to 20mhz): 2.5ps (typical) offset noise p o w er 100hz ................. -90.5 dbc/hz 1khz ............... -114.2 dbc/hz 10khz ............... -123.6 dbc/hz 100khz ............... -128.1 dbc/hz ? 3.3v supply voltage ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free rohs (6) packages 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 xtal2 test_clk xtal_sel v cca s_load s_data s_clock mr m5 m6 m7 m8 n0 n1 nc v ee v ee nfout0 fout0 v cco nfout1 fout1 v cc test xtal1 np_load vco_sel m0 m1 m2 m3 m4 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view ics84320-01 hiperclocks? ic s osc vco_sel xtal_sel test_clk xtal1 xtal2 s_load s_data s_clock np_load m0:m8 n0:n1 vco pll fout0 nfout0 fout1 nfout1 test configuration interface logic m 0 1 0 1 phase detector 1 2 4 8 mr n 32-lead vfqfn 5mm x 5mm x 0.925 package body k package top view
84320ay-01 2 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer note: the functional description that follows describes op- eration using a 25mhz crystal. valid pll loop divider values for different crystal or input frequencies are defined in the in- put frequency characteristics, table 5, note 1. the ics84320-01 features a fully integrated pll and there- fore requires no external components for setting the loop band- width. a fundamental crystal is used as the input to the on- chip oscillator. the output of the oscillator is fed into the phase detector. a 25mhz crystal provides a 25mhz phase detector reference frequency. the vco of the pll operates over a range of 620mhz to 780mhz. the output of the m divider is also applied to the phase detector. the phase detector and the m divider force the vco output fre- quency to be m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by a divider prior to being sent to each of the lvpecl output buffers. the divider provides a 50% output duty cycle. the programmable features of the ics84320-01 support two input modes to program the m divider and n output divider. the two input operational modes are parallel and serial. figure 1 shows the timing diagram for each mode. in parallel mode, the np_load input is initially low. the data on inputs m0 through m8 and n0 and n1 is passed directly to the m divider and n output divider. on the low-to-high transition of the np_load input, the data is latched and the m divider remains loaded until the next low transition on np_load or until a serial event occurs. as a result, the m and n bits can be hardwired to set the m divider and n output divider to a specific default state that will auto- matically occur during power-up. the test output is low when operating in the parallel input mode. the relation-ship between the vco frequency, the crystal frequency and the m divider is defined as follows: the m value and the required values of m0 through m8 are shown in table 3b to program the vco frequency function table. valid m values for which the pll will achieve lock for a 25mhz reference are defined as 25 m 31. the frequency out is defined as follows: serial operation occurs when np_load is high and s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider and n output di- vider when s_load transitions from low-to-high. the m divide and n output divide values are latched on the high-to- low transition of s_load. if s_load is held high, data at the s_data input is passed directly to the m divider and n output divider on each rising edge of s_clock. the serial mode can be used to program the m and n bits and test bits t1 and t0. the internal registers t0 and t1 determine the state of the test output as follows: f unctional d escription fvco = fxtal x m t1 t0 test output 0 0 low 0 1 s_data, shift register input 1 0 output of m divider 1 1 cmos fout f igure 1. p arallel & s erial l oad o perations *note: the null timing slot must be observed. time s erial l oading p arallel l oading t s t h t s t h t s m, n t1 t0 * null n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m 0 s_clock s_data s_load np_load m0:m8, n0:n1 np_load s_load fout = fvco = fxtal x m n n
84320ay-01 3 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 15 mt u p n ip u l l u p f o n o i t i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i d a o l _ p n , 4 , 3 , 2 , 9 2 , 8 2 2 3 , 1 3 , 0 3 , 8 m , 7 m , 6 m , 1 m , 0 m 4 m , 3 m , 2 m t u p n in w o d l l u p 6 , 51 n , 0 nt u p n in w o d l l u p , c 3 e l b a t n i d e n i f e d s a e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a t n o i t c n u f 7c nd e s u n u. t c e n n o c o n 6 1 , 8v e e r e w o p. s n i p y l p p u s e v i t a g e n 9t s e tt u p t u o . n o i t a r e p o f o e d o m l a i r e s e h t n i e v i t c a s i h c i h w t u p t u o t s e t . e d o m l e l l a r a p n i w o l n e v i r d t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 1v c c r e w o p. n i p y l p p u s e r o c 2 1 , 1 11 t u o f n , 1 t u o ft u p t u o . s l e v e l e c a f r e t n i l c e p v l . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 3 1v o c c r e w o p. n i p y l p p u s t u p t u o 5 1 , 4 10 t u o f n , 0 t u o ft u p t u o . s l e v e l e c a f r e t n i l c e p v l . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 7 1r mt u p n in w o d l l u p l a n r e t n i e h t s e c r o f , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a e h t d n a w o l o g o t x t u o f s t u p t u o e u r t e h t g n i s u a c t e s e r e r a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t x t u o f n s t u p t u o d e t r e v n i t o n s e o d r m f o n o i t r e s s a . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s e u l a v t d n a , n , m d e d a o l t c e f f a 8 1k c o l c _ st u p n in w o d l l u p r e t s i g e r t f i h s e h t o t n i t u p n i a t a d _ s t a t n e s e r p a t a d l a i r e s n i s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o e g d e g n i s i r e h t n o 9 1a t a d _ st u p n in w o d l l u p f o e g d e g n i s i r e h t n o d e l p m a s a t a d . t u p n i l a i r e s r e t s i g e r t f i h s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s 0 2d a o l _ st u p n in w o d l l u p . s r e d i v i d e h t o t n i r e t s i g e r t f i h s m o r f a t a d f o n o i t i s n a r t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 2v a c c r e w o p. n i p y l p p u s g o l a n a 2 2l e s _ l a t xt u p n ip u l l u p . e c r u o s e c n e r e f e r l l p e h t s a s t u p n i t s e t r o l a t s y r c n e e w t e b s t c e l e s . w o l n e h w k l c _ t s e t s t c e l e s . h g i h n e h w s t u p n i l a t x s t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 2k l c _ t s e tt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c t s e t 5 2 , 4 21 l a t x , 2 l a t xt u p n i . t u p t u o e h t s i 2 l a t x . t u p n i e h t s i 1 l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c 6 2d a o l _ p nt u p n in w o d l l u p s i 0 m : 8 m t a t n e s e r p a t a d n e h w s e n i m r e t e d . t u p n i d a o l l e l l a r a p e h t s t e s 0 n : 1 n t a t n e s e r p a t a d n e h w d n a , r e d i v i d m o t n i d e d a o l . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e u l a v r e d i v i d t u p t u o n 7 2l e s _ o c vt u p n ip u l l u p . e d o m s s a p y b r o l l p n i s i r e z i s e h t n y s r e h t e h w s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
84320ay-01 4 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 3a. p arallel and s erial m ode f unction t able s t u p n i s n o i t i d n o c r md a o l _ p nmnd a o l _ sk c o l c _ sa t a d _ s hx xxx x x . w o l s t u p t u o s e c r o f . t e s e r ll a t a da t a dx x x m e h t o t y l t c e r i d d e s s a p s t u p n i n d n a m n o a t a d . w o l d e c r o f t u p t u o t s e t . r e d i v i d t u p t u o n d n a r e d i v i d l a t a da t a dl x x d e d a o l s n i a m e r d n a s r e t s i g e r t u p n i o t n i d e h c t a l s i a t a d . s r u c c o t n e v e l a i r e s a l i t n u r o n o i t i s n a r t w o l t x e n l i t n u lh xxl a t a d n o a t a d h t i w d e d a o l s i r e t s i g e r t f i h s . e d o m t u p n i l a i r e s . k c o l c _ s f o e g d e g n i s i r h c a e n o a t a d _ s lh xx la t a d e h t o t d e s s a p e r a r e t s i g e r t f i h s e h t f o s t n e t n o c . r e d i v i d t u p t u o n d n a r e d i v i d m lh xx la t a d. d e h c t a l e r a s e u l a v r e d i v i d t u p t u o n d n a r e d i v i d m lh xxl x x . s r e t s i g e r t f i h s t c e f f a t o n o d t u p n i l a i r e s r o l e l l a r a p lh xxh a t a d. d e k c o l c s i t i s a r e d i v i d m o t y l t c e r i d d e s s a p a t a d _ s w o l = l : e t o n h g i h = h e r a c t ' n o d = x n o i t i s n a r t e g d e g n i s i r = n o i t i s n a r t e g d e g n i l l a f = t able 3b. p rogrammable vco f requency f unction t able t able 3c. p rogrammable o utput d ivider f unction t able s t u p n i e u l a v r e d i v i d n ) z h m ( y c n e u q e r f t u p t u o 1 n0 nm u m i n i mm u m i x a m 00 1 0 2 60 8 7 01 2 0 1 30 9 3 10 4 5 5 15 9 1 11 8 5 . 7 75 . 7 9 y c n e u q e r f o c v ) z h m ( e d i v i d m 6 5 28 2 14 62 36 18421 8 m7 m6 m5 m4 m3 m2 m1 m0 m 5 2 65 2 000011001 ? ? ????????? 0 0 78 2 0000 11100 ? ? ????????? 5 7 71 3 0000 11111 y c n e u q e r f t u p n i k l c _ t s e t r o l a t s y r c o t d n o p s e r r o c s e i c n e u q e r f g n i t l u s e r e h t d n a s e u l a v e d i v i d m e s e h t : 1 e t o n . z h m 5 2 f o
84320ay-01 5 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 4a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n i e g a t l o v h g i h , r m , l e s _ l a t x , l e s _ o c v , 1 n : 0 n , d a o l _ p n , d a o l _ s 8 m : 0 m , k c o l c _ s , a t a d _ s 2v c c 3 . 0 +v k l c _ t s e t2v c c 3 . 0 +v v l i t u p n i e g a t l o v w o l , r m , l e s _ l a t x , l e s _ o c v , 1 n : 0 n , d a o l _ p n , d a o l _ s 8 m : 0 m , k c o l c _ s , a t a d _ s 3 . 0 -8 . 0v k l c _ t s e t3 . 0 -3 . 1v i h i t u p n i t n e r r u c h g i h , r m , 1 n , 0 n , 8 m - 6 m , 4 m - 0 m , k l c _ t s e t , k c o l c _ s d a o l _ p n , d a o l _ s , a t a d _ s v c c v = n i v 5 6 4 . 3 =0 5 1a l e s _ o c v , l e s _ l a t x , 5 mv c c v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , r m , 1 n , 0 n , 8 m - 6 m , 4 m - 0 m , k l c _ t s e t , k c o l c _ s d a o l _ p n , d a o l _ s , a t a d _ s v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a l e s _ o c v , l e s _ l a t x , 5 m v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a v h o t u p t u o e g a t l o v h g i h 1 e t o n ; t s e t6 . 2v v l o t u p t u o e g a t l o v w o l 1 e t o n ; t s e t 5 . 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n av c c 2 2 . 0 ?3 . 35 6 4 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i e e t n e r r u c y l p p u s r e w o p 5 5 1a m i a c c t n e r r u c y l p p u s g o l a n a 2 2a m note 1: outputs terminated with 50 to v cco /2. a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, v o (lvcmos) -0.5v to v cco + 0.5v outputs, i o (lvpecl) continuous current 50ma surge current 100ma package thermal impedance, ja 32 lead lqfp 47.9c/w (0 lfpm) 32 lead vfqfn 34.8c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
84320ay-01 6 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 4c. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o c c , n o i t c e s " n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p " e e s . v 2 - . " t i u c r i c t s e t d a o l t u p t u o v 3 . 3 " t able 5. i nput f requency c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i 1 e t o n ; k l c _ t s e t4 10 4z h m 1 e t o n ; 2 l a t x , 1 l a t x4 10 4z h m k c o l c _ s 0 5z h m e h t n i h t i w e t a r e p o o t o c v e h t r o f t e s e b t s u m e u l a v m e h t , e g n a r y c n e u q e r f k l c _ t s e t d n a l a t s y r c t u p n i e h t r o f : 1 e t o n 5 4 e r a m f o s e u l a v d i l a v , z h m 4 1 f o y c n e u q e r f t u p n i m u m i n i m e h t g n i s u . e g n a r z h m 0 8 7 o t z h m 0 2 6 m e h t g n i s u . 5 5 6 1 e r a m f o s e u l a v d i l a v , z h m 0 4 f o y c n e u q e r f m u m i x a m m . 9 1 t able 6. c rystal c haracteristics t able 7. ac c haracteristics , v cc = v cca = v cco = 3.3v5%, t a = 0c to 70c r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 4 10 4z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o5 . 7 70 8 7z h m t ) r e p ( t i j1 e t o n ; s m r , r e t t i j d o i r e pz h m 0 0 1 > t u o f0 . 26 . 2s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r , z h m 2 5 . 5 5 1 z h m 0 2 - z h k 2 1 5 . 2s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 5 1s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 10 0 6s p t s e m i t p u t e s d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n t h e m i t d l o h d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n c d oe l c y c y t u d t u p t u o 1 > n9 41 5% t u o f 5 2 65 45 5% t w p h t d i w e s l u p t u p t u o5 2 6 > ?t pd o i r e 0 5 1 - 2 /t pd o i r e 0 5 1 + 2 /s p t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . s t u p n i l a t x g n i s u e c n a m r o f r e p r e t t i j : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
84320ay-01 7 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t ypical p hase n oise at 155.52mh z t ypical p hase n oise at 622.08mh z o ffset f requency (h z ) dbc hz n oise p ower 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 1 10 100 1k 10k 100k 1m 10m 100m 155.52mhz rms phase jitter (random) 12khz to 20mhz = 2.5ps (typical) phase noise result by adding sonet bandpass filter to raw data raw phase noise data oc-48 sonet bandpass filter o ffset f requency (h z ) dbc hz n oise p ower 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 622.08mhz rms phase jitter (random) 12khz to 20mhz = 2.48ps (typical) phase noise result by adding sonet bandpass filter to raw data raw phase noise data oc-48 sonet bandpass filter 1 10 100 1k 10k 100k 1m 10m 100m ? ? ? ? ? ?
84320ay-01 8 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer p arameter m easurement i nformation p eriod j itter o utput s kew 3.3v o utput l oad ac t est c ircuit scope qx nqx lvpecl 2v o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram -1.3v 0.165v t sk(o) nfoutx foutx nfouty fouty clock outputs 20% 80% 80% 20% t r t f v sw i n g pulse width t period t pw t period odc = foutx nfoutx v cc , v cco v cca 2v v ee
84320ay-01 9 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics84320-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 24 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. the 24 resistor can also be replaced by a ferrite bead. p ower s upply f iltering t echniques f igure 2. p ower s upply f iltering 24 v cca 10 f .01 f 3.3v .01 f v cc i nputs : c rystal i nputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. test_clk i nput for applications not requiring the use of the test clock, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the test_clk to ground. lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
84320ay-01 10 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer c rystal i nput i nterface a crystal can be characterized for either series or parallel mode operation. the ics84320-01 has a built-in crystal oscillator circuit. this interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy f igure 3. c rystal i npu t i nterface suitable for most applications. additional accuracy can be achieved by adding two small capacitors c1 and c2 as shown in figure 3 . c2 22p c1 18p x1 18pf parallel crystal ics84320-01 25 24 xtal1 xtal2 lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 4. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output impedance of the driver (ro) plus the f igure 4. g eneral d iagram for lvcmos d river to xtal i nput i nterface series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . xtal_in xtal_out ro rs zo = ro + rs 50 0.1f r1 r2 v dd v dd
84320ay-01 11 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termi- nation for lvpecl outputs. the two different layouts men- tioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, ter- minating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched imped- f igure 5b. lvpecl o utput t ermination f igure 5a. lvpecl o utput t ermination ance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs
84320ay-01 12 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer the schematic of the ics84320-01 layout example used in this layout guideline is shown in figure 6a. the ics84320- 01 recommended pcb board layout for this example is shown in figure 6b. this layout example is used as a gen- l ayout g uideline f igure 6a. s chematic of r ecommended l ayout eral guideline. the layout in the actual system will depend on the selected component types, the density of the compo- nents, the density of the traces, and the stack up of the p.c. board. r4 84 c16 10u + - c11 0.01u ref_in c14 0.1u vcc in+ tl1 zo = 50 ohm c1 s_clock vcca vcc fout vcc u1 ics84320-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 m5 m6 m7 m8 n0 n1 nc vee test vcc fout1 nfout1 vcco fout0 nfout0 vee mr s_clock s_data s_load vcca nxtal_sel t_c lk xta l 2 m4 m3 m2 m1 m0 vco_sel np_load xtal1 s_data tl2 zo = 50 ohm x1 c2 s_load r7 24 xtal_sel foutn in- r3 125 r1 125 r2 84 c15 0.1u vcc
84320ay-01 13 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer f igure 6b. pcb b oard l ayout for ics84320-01 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors c14 and c15, as close as pos- sible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted inductance between the decoupling ca- pacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v cca pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the differential 50 output traces should have the same length. ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock traces on the same layer. whenever pos- sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. ? make sure no other signal traces are routed between the clock trace pair. ? the matching termination resistors should be located as close to the receiver input pins as possible. c rystal the crystal x1 should be located as close as possible to the pins 25 (xtal1) and 24 (xtal2). the trace length between the x1 and u1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. other signal traces should not be routed near the crystal traces. tl1, tl21n are 50 ohm traces and equal length r2 via tl1n gnd c15 r4 tl1 r1 tl1 x1 vcc c11 pin 1 c1 c14 tl1n c2 r3 c16 r7 close to the input pins of the receiver u1 vcca
84320ay-01 14 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer f igure 7. p.c.a ssembly for e xposed p ad t hermal r elease p at h ?s ide v iew (d rawing not to s cale ) vfqfn epad t hermal r elease p ath in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 7. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/ electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadfame base package, amkor technology. thermal via land pattern solder pin solder pin pad pin pad pin ground plane exposed heat slug (ground pad)
84320ay-01 15 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics84320-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics84320-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 155ma = 537.08mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.465v, with all outputs switching) = 537.1mw + 60mw = 597.1mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 8a below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.597w * 42.1c/w = 95.1c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 8a. t hermal r esistance ja for 32- pin lqfp, f orced c onvection ja by velocity (linear feet per minute) t able 8b. t hermal r esistance ja for 32- pin vfqfn f orced c onvection 0 multi-layer pcb, jedec standard test boards 34.8c/w
84320ay-01 16 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 8. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ) * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ) * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 8. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
84320ay-01 17 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer r eliability i nformation t ransistor c ount the transistor count for ics84320-01 is: 3776 t able 9a. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 9b. ja vs . a ir f low t able for 32 l ead vfqfn p ackage ja by velocity (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 34.8c/w
84320ay-01 18 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer p ackage o utline - y s uffix for 32 l ead lqfp t able 10a. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
84320ay-01 19 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer p ackage o utline - 32 l ead k p ackage t able 10b. p ackage d imensions reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 2 3 a 0 8 . 00 . 1 1 a 05 0 . 0 3 a e c n e r e f e r 5 2 . 0 b 8 1 . 00 3 . 0 e c i s a b 0 5 . 0 n d 8 n e 8 d 0 . 5 2 d 5 2 . 15 2 . 3 e 0 . 5 2 e 5 2 . 15 2 . 3 l 0 3 . 00 5 . 0 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref. ) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 10b below.
84320ay-01 20 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t able 11. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - y a 0 2 3 4 8 s c i1 0 - y a 0 2 3 4 8 s c ip f q l d a e l 2 3y a r tc 0 7 o t c 0 t 1 0 - y a 0 2 3 4 8 s c i1 0 - y a 0 2 3 4 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 0 7 o t c 0 n l 1 0 - y a 0 2 3 4 8 s c in 1 0 a 0 2 3 4 8 s c ip f q l " d e l a e n n a / e e r f - d a e l " d a e l 2 3y a r tc 0 7 o t c 0 t n l 1 0 - y a 0 2 3 4 8 s c in 1 0 a 0 2 3 4 8 s c ip f q l " d e l a e n n a / e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 0 7 o t c 0 1 0 - k a 0 2 3 4 8 s c i1 0 k a 0 2 3 4 8 s c in f q f v d a e l 2 3y a r tc 0 7 o t c 0 t 1 0 - k a 0 2 3 4 8 s c i1 0 k a 0 2 3 4 8 s c in f q f v d a e l 2 3l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l 1 0 - k a 0 2 3 4 8 s c il 1 0 a 0 2 3 4 s c in f q f v " e e r f - d a e l " d a e l 2 3y a r tc 0 7 o t c 0 t f l 1 0 - k a 0 2 3 4 8 s c il 1 0 a 0 2 3 4 s c in f q f v " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 5 2c 0 7 o t c 0 s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " n l r o " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n . t n a i l p m o c while the information presented herein has been checked for both accur acy and reliability, integrated de vice technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature ranges, high reliability or other extraordina ry environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments.
84320ay-01 21 rev. c october 22, 2007 ics84320-01 780mh z , c rystal - to -3.3v d ifferential lvpecl f requency s ynthesizer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a7 . t a m r o f d n a s t o l p e s i o n e s a h p l a c i p y t d e t a d p u 4 0 / 2 / 7 a1 1 t6 1 . r e b m u n r e d r o / t r a p e e r f d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 4 0 / 4 2 / 8 b a 4 t 6 t 1 1 t 1 5 6 8 9 0 1 8 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f o t v 5 3 1 . 3 m o r f . n i m a c c v d e t a d p u - s c i t s i r e t c a r a h c c d y l p p u s r e w o p v c c . 2 2 . 0 ? . l e v e l e v i r d d e d d a - e l b a t s c i t s i r e t c a r a h c l a t s y r c . m a r g a i d t i u c r i c t s e t c a d a o l t u p t u o v 3 . 3 d e t c e r r o c d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r d e d d a . e c a f r e t n i l a t x o t s o m c v l . r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o . t e e h s a t a d e h t t u o h g u o r h t e g a k c a p n f q f v d e d d a 6 0 / 4 1 / 4 c c 4 t6 5 1 - 4 1 v d e t c e r r o c - e l b a t s c i t s i r e t c a r a h c c d l c e p v l h o v m o r f . x a m o c c o t v 0 . 1 ? v o c c . v 9 . 0 ? v t c e l f e r o t n o i t a p i s s i d r e w o p d e t c e r r o c - s n o i t a r e d i s n o c r e w o p h o e l b a t n i x a m . c 4 7 0 / 0 1 / 4 c 1 1 t 4 1 9 1 d e d d a . n o i t c e s h t a p e s a e l e r l a m r e h t d a p e n f q f v . g n i k r a m e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 7 0 / 2 2 / 0 1

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